1. Field of the Invention
This invention relates generally to the testing of digital signal processing units and, more particularly, to the signals that are transmitted from a target processor to a host processing to permit analysis of the target processor operation. Certain events in the target processor must be communicated to the host processing unit along with contextual information. In this manner, the test and debug data can be analyzed and problems in the operation of the target processor identified.
2. Description of the Related Art
As microprocessors and digital signal processors have become increasingly complex, advanced techniques have been developed to test these devices. Dedicated apparatus is available to implement the advanced techniques. Referring to FIG. 1A, a general configuration for the test and debug of a target processor 12 is shown. The test and debug procedures operate under control of a host processing unit 10. The host processing unit 10 applies control signals to the emulation unit 11 and receives (test) data signals from the emulation unit 11 by cable connector 14. The emulation unit 11 applies control signals to and receives (test) signals from the target processing unit 12 by connector cable 15. The emulation unit 11 can be thought of as an interface unit between the host processing unit 10 and the target processor 12. The emulation unit 11 processes the control signals from the host processor unit 10 and applies these signals to the target processor. 12 in such a manner that the target processor will respond with the appropriate test signals. The test signals from the target processor 12 can be a variety types. Two of the most popular test signal types are the JTAG (Joint Test Action Group) signals and trace signals. The JTAG protocol provides a standardized test procedure in wide use in which the status of selected components is determined in response to control signals from the host processing unit. Trace signals are signals from a multiplicity of selected locations in the target processor 12 during defined period of operation. While the width of the bus 15 interfacing to the host processing unit 10 generally has a standardized dimension, the bus between the emulation unit 11 and the target processor 12 can be increased to accommodate an increasing amount of data needed to verify the operation of the target processing unit 12. Part of the interface function between the host processing unit 10 and the target processor 12 is to store the test signals until the signals can be transmitted to the host processing unit 10.
Referring to FIG. 1B, the operation of the trigger generation unit 19 is shown. The trigger unit provides the main component by which the operation/state of the target processor can be altered. At least one event signal is applied to the trigger generation unit 19. Based on the identity of the event signal(s) applied to the trigger generation unit 19, a trigger signal is selected. Certain events and combination of events, referred to as an event front, generate a selected trigger signal that results in certain activity in the target processor such as a debug halt. Combinations of different events generating trigger signals are referred to as jobs. Multiple jobs can have the same trigger signal or combination of trigger signals. In the test and debug of the target processor, the trigger signals can provide impetus for changing state in the target processor or for performing a specified activity. The event front defines the reason for the generation of trigger signal. This information is important in understanding the operation of the target processor because, as pointed out above, several combinations of events can result in the generation of a trigger signal.
In order to analyze the operation of the target processing unit, the portion of the code resulting in the trigger signal must be identified. However, the events in the host processor leading to the generation of event signals can be complicated. Specifically, the characteristics of an instruction at a program counter address can determine whether a trigger signal should be generated. A trigger signal can be an indication of when an address is within a range of addresses, outside of a range of addresses, some combination of address characteristics, and/or the address is aligned with a reference address. In this instance, the address can be the program address of an instruction or a memory address directly or indirectly referenced by a program instruction.
In testing the target processors, certain events must be identified. The debug halt signal is generated when specified conditions within the target processor indicates that an event has occurred that requires analysis of the target processor operation. However, it is important to determine the point in the processing procedure where the debug halt condition signal was generated. In additions, the relationship of the debug halt signal to the target processor clock, to the program execution, and to the data generated as a result of the program execution can be needed by the host processing unit to determine the origin of the debug halt.
A need has been felt for apparatus and an associated method having the feature that a debug halt signal is identified in a target processor and generation of the debug halt signal is communicated to the testing apparatus. It is another feature of the apparatus and associated method to transfer information concerning the generation of the debug halt procedure the testing processing unit using a trace stream. It is a still further feature of the apparatus and associated method to communicate to the testing apparatus where the debug halt signal is initiated during the program execution. It is yet another feature of the present in invention to communicate to the testing processing unit the relationship of the generation of the debug halt signal to the target processor clock.